1. Field of the Invention
The invention relates to a method of fabricating a glue layer of a contact/via, and more particularly to a method of fabricating a glue layer of a contact/via without an overhang structure on the upper corner of the contact/via.
2. Description of the Related Art
Currently, semiconductor devices are widely involved in many products and services in our daily life. All these semiconductor devices are fabricated on a wafer through many processes, such as photolithography, deposition, ion implantation, or etching, to form an integrated circuit (IC) device. One wafer usually includes a large number of IC devices.
In semiconductor fabrication on a wafer, or on a substrate, an opening with a high aspect ratio, which is defined as a ratio of the depth to the width, is needed in some situations. The opening, such as a via opening or a contact opening, is formed in a dielectric layer and is filled with a metallic material, such as tungsten, to form a metal plug. The dielectric layer is usually sandwiched between two metal layers or between one metal layer on the top and the substrate on the bottom. The purpose of the metal plug is to interconnect these two metal layers or the upper metal layer and the substrate to achieve an interconnection between device elements. Since the material properties of the meal plug and the dielectric layer are different, there is usually a poor adhesion between the metal plug and the dielectric layer. In order to improve the adhesion between the metal plug and the dielectric layer, a conformal glue layer/barrier layer, is usually formed over the opening before the metal plug is filled in the opening. The glue layer can improve adhesion between the metal plug and the dielectric layer.
Currently, the glue layer typically includes a layer of titanium and titanium nitride as shown in FIG. 1A and FIG. 1B, which are cross-sectional views, illustrating a fabrication process of an conventional opening plug. In FIG. 1A, a dielectric layer 102 is formed on a substrate 100. An opening 104 is formed in the dielectric layer 102. A titanium layer 106 is formed over the substrate 100 by physical vapor deposition (PVD) and a titanium nitride layer 108 is formed over the titanium layer 106 by chemical vapor deposition (CVD). The titanium layer 106 and the titanium nitride layer 108 are formed together as a glue layer, which is conformal to the substrate 100. Since a high integration IC device is desired, the aspect ratio of the opening is usually high, which degrades the step coverage performance. The titanium layer 106 formed by PVD may have an overhang 106a on upper corner 102a of the opening 104.
In FIG. 1B, a tungsten metal layer 110 is formed over the substrate 100 to fill the opening 104 shown in FIG. 1A. The formation of the overhang 106a worsens the step coverage performance. A void 112 is formed within the metal layer 110 filling the opening 104. The void 112 can induce some problems, such as fracture of the metal layer 110 or high resistance of the metal layer 110, and cause a failure of the device.